(1) Field of the Invention
The present invention relates to methods used to fabricate dynamic random access memory, (DRAM), semiconductor devices, and more specifically to a method used to create contact structures to peripheral regions, while simultaneously forming the capacitor node structure, for a DRAM memory cell.
(2) Description of the Prior Art
As the density of DRAM chips increase to giga-bit levels, the area of the DRAM cell has to be decreased. The reduced area of the DRAM cell, is achieved using design rules of about 0.15 micrometers, or less. This aggressive design rule, places demands on the specific components of the DRAM cell, and of peripheral regions, of the DRAM chip. For example, in order to achieve desired performance, the capacitance of the DRAM device has to be maintained via the use of capacitor nodes, exhibiting a height of at least 1 micrometer. The thick insulator layers used to passivate the tall, capacitor structures, result in process complexities, when attempting to open contact holes to a lower feature of a DRAM capacitor structure. In addition the thick insulator layers also result in high aspect ratio contact, or via holes, used for communication between interconnect structures, and substrate components, in the peripheral region of the DRAM chip. This invention will describe a novel process utilizing a dual damascene procedure, in which the first damascene procedure, results in the simultaneous creation of the tall capacitor nodes, in the DRAM cell region, and a lower interconnect structure, in the peripheral region. A second damascene procedure allows the creation of metal filled, narrow via holes, to the DRAM capacitor structure, as well as to the lower interconnect structure, to be realized. Prior art, such as Chou et al, in U.S. Pat. No. 5,731,236, as well as Jeng et al, in U.S. Pat. No. 5,710,073, show combinations of capacitor structures, self-aligned contact, (SAC), structures, and interconnect structures, however none of these prior arts offer the dual damascene procedures, used in the present invention, featuring the simultaneous formation of the DRAM cell, capacitor node structures, and the interconnect structures, used in the peripheral region of the DRAM chip.